In recent years, the development of portable telecommunication equipment and laptop computers has become a major driving force in the design and technology of the semiconductor IC. One of the most attractive features of the semiconductor IC is a very high-density non-volatile mask ROM. To achieve very high-density mask ROM. a novel semiconductor mask ROM technology incorporating a vertical cell is aiming at this objective and was proposed by Bertagnoili et al. in the reference, B. Bertagnoill et al., "ROS: An Extremely High Density Mask ROM Technology Based On Vertical Transistor Cells", Symp. on VLSI Tech. Dig., p. 58, 1996. The key of this technology is a cell concept based on a vertical MOS transistor in a trench which allows use of the bottom of the trench as an additional self-aligned bit line, and thus doubling the bit line density. This technology enables an approximately twofold packing density compared to conventional planar ROM.
An alternative method to doubling the storage capacity is using a novel multi-state (.gtoreq.3 kinds of state) concept. Such a memory cell can double the storage capacitor without Increasing chip area. For example, if memory cells store only data "Q" and "1" states, a more great number of mask ROM cell transistors. should be demanded to provide storage data as compared with that of memory cells which can store four kinds of states, called multiple state mask ROM cells.
A conventional multi-value ROM stores more than three states, in the manner that changes the threshold, voltage of memory cell transistors given by Sheng et al. in U.S. Patent No. 5,585,297 issued Dec. 17, 1996. A plurality of ion implantation stages using boron ions is performed incorporating a plurality of different mask patterns and different dosage levels. However, the high dose boron coding implant will result in a lower junction breakdown performance of the coded MOSFET and a very high band-to-band leakage current between the adjacent cells as stated in the reference U.S. Patent No. 5,683,925, to Irani et al., issued on Nov. 4, 1997. Hence, Irani et al. in their patent proposed a method for fabricating the mask ROM. In this method, a thick gate oxide layer 18 is thermally grown within a ROM array area 30, even though the gate oxide 2 in the periphery 32 is thinner, as shown in FIG. 1.
An alternative method is proposed by Takiziaws at al. in U.S, Patent No. 5,556,800 issued on Sep. 17, 1996. Takizlawa et al., propose on the contrary, a manner that varies the gate insulating layer's thickness to change the threshold voltage of the channel region. The channel region is divided into dual parts: one divided part having a different gate oxide thickness from the other, and thus a different transitivity for ion implantation. Specifically, the gate electrode has different characteristics of a drain current corresponding to a gate voltage (I.sub.D -V.sub.G) in the channel regions adjacent to each other.